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RT5021 ? ds5021-01 april 2013 www.richtek.com 1 copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? 6 + 3 channels dc/dc pmu with li-ion battery charger for cmos dsc/dv general description the RT5021 is a complete power supply solution for digital still cameras and other hand held devices. the RT5021 is composed of a multi-channel dc/dc power converter unit, a single-cell linear li-ion battery charger, a charger type detector, and an i 2 c control interface. the power converter unit includes one synchronous step- up converter (ch1), one synchronous step-up/down converter (ch2), three synchronous step-down converters (ch3/4/5), two ldos with input power as low as 1.5v (ch6/8), one wled driver in synchronous high-voltage step-up mode or low-voltage current regulator mode (ch7), and a keep-alive ldo (ch9) for rtc application. all converters are internally frequency compensated and integrate power mosfets. the power converter unit provides complete protection functions : over current, thermal shutdown, over voltage, and under voltage protection. RT5021 has a wakeup impulse generation circuitry to monitor vin or bat installation event. to fulfill most of applications, RT5021 has six preset power on/off sequences. the battery charger includes auto power path management (appm). no external mosfets are required. the charger can enter sleep mode when power is removed. simplified application circuit charging tasks are optimized by using a control algorithm to vary the charge rate, including pre-charge mode, fast charge mode and constant voltage mode. the charge current can also be programmed via the i 2 c control interface. the battery regulation voltage and current can be adjusted by jeita standard temperature control or other schemes set via the i 2 c interface. the internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures. the charging task will always be terminated in constant voltage mode when the charging current reduces to the termination current of 10% x i chg_fast . the charger includes under voltage and over voltage protection for the supply input voltage, vin. the charger includes usb charger detection circuitry via d+ and d- pins of usb interface to detect usb standard downstream ports (sdp), usb charging downstream port (cdp), dedicated charger port (dcp), or apple/sony charger ports. RT5021 uses some indicators to show charger states : two open drain ports chg and chg2, and an interrupt (int) to immediately notify the state change. RT5021 has i 2 c interface to control rich functions of power converter unit and charger unit. the RT5021 is available in the wqfn-40l 5x5 package. vin sys gnd pvd1 adapter/usb RT5021 scl sda i 2 c control vo2 lx3 lx4 lx5 vo6 pvd7 vo8 vrtc step-up for motor step-up/down for i/o step-down for core step-down for memory step-down ldo step-up for led backlight ldo ldo for rtc system power bat charger for battery
RT5021 2 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ` ` ` ` ` seq # 4 : ch1 ch4 ch3 ch2 ` ` ` ` ` seq # 5 : ch1 ch4 ch2 ch3 z z z z z all power switches integrated with internal compensation z z z z z discharge output of every channels when turning off z z z z z wake up impulse to monitor bat and vin plug-in z z z z z fixed 2mhz switching frequency for ch1/3/4/5, fixed 1mhz switching frequency for ch2/7 charger unit z z z z z 28v maximum rating for v in power z z z z z selectable power input current limit (0.1a / 0.5a / 1a / 1.5a) z z z z z auto power path management (appm) with integrated power mosfets z z z z z battery charging current control and regulation voltage control z z z z z programmable charging current and safe charge timer z z z z z optimized charge rate via thermal feedback z z z z z under voltage protection, over voltage protection z z z z z charger status and vin power good indicators z z z z z interrupt indicator to jeita temperature/fault/ status events when pmu is enabled ` ` ` ` ` battery temperature events ` ` ` ` ` battery removing event ` ` ` ` ` charger in thermal regulation control ` ` ` ` ` safety timer timeout ` ` ` ` ` end of charging ` ` ` ` ` vin power good ` ` ` ` ` vin < dpm threshold 4.35v ` ` ` ` ` charger type detection finishing z z z z z charger type detection ` ` ` ` ` dedicated charger : support apple and sony charger ` ` ` ` ` secondary charger detection to distinguish cdp and dcp z z z z z i 2 c control interface : support fast mode up to 400kb/s z z z z z small 40-lead wqfn package z z z z z rohs compliant and halogen free features power converter unit z z z z z ch1 lv sync step-up ` ` ` ` ` support up to 1a loading, dvs (dynamic voltage scaling), load-disconnect, up to 95% efficiency, psm/pwm selectable z z z z z ch2 lv sync step-up/down ` ` ` ` ` support up to 1a loading, dvs, up to 95% efficiency, psm/pwm selectable z z z z z ch3/4 lv sync step-down ` ` ` ` ` support up to 1.3a loading, dvs, up to 95% efficiency, 100% (max) duty cycle, psm/pwm selectable z z z z z ch5 lv sync step-down ` ` ` ` ` support up to 0.6a loading, up to 95% efficiency, 100% (max) duty cycle ` ` ` ` ` output voltage can be selected from preset list or set by external feedback network z z z z z ch6 low input power ldo ` ` ` ` ` v in range 1.5v to 5.5v ` ` ` ` ` output voltage level selectable in i 2 c register z z z z z ch7 wled driver in either sync step-up operation or current regulator operation ` ` ` ` ` step-up mode with led open protection (ovp7 16v or 25v, selectable in i 2 c register) ` ` ` ` ` step-up mode support series 2 to 6 wled and load disconnect function ` ` ` ` ` current regulator mode for 1 wled ` ` ` ` ` 31 wled dimming levels ` ` ` ` ` automatic mode selection by external circuit topology z z z z z ch8 generic ldo ` ` ` ` ` v in range 1.5v to 5.5v ` ` ` ` ` output voltage level selectable in i 2 c register z z z z z ch9 low quiescent ldo with reverse leakage prevention for rtc power supply ` ` ` ` ` fixed 3.05v output z z z z z six preset power on/off sequences by one pin seq ` ` ` ` ` seq # 0 : ch2 ch3 ch4 ` ` ` ` ` seq # 1 : ch1 ch3 ch2 ch4 ` ` ` ` ` seq # 2 : ch1 ch3 ch4 ch2 ` ` ` ` ` seq # 3 : ch1 ch2 ch4 ch3
RT5021 3 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications z dsc power supply system z cmos-sensor dv z portable instruments pin configurations (top view) wqfn-40l 5x5 wake lx1 pvd6 vo6 lx7 fb7 pvd7 pvd1 vp pvd2 fb3 scl vo8 fb2 vo2 lx2a lx2b ts 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 fb4 seq lx4 en pvd45 lx5 vo5/fb5 pvd8 sda vrtc dn dp vin sys sys bat bat pvd3 lx3 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 gnd chg2 chg int marking information RT5021 package type qw : wqfn-40l 5x5 (w-type) lead plating system g : green (halogen free and pb free) RT5021 gqw ymdnn RT5021gqw : product number ymdnn : date code
RT5021 4 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? functional pin description pin no. pin name pin function 1 wake wake-up impulse push pull output. if vin or bat plug in, wake pin generates one 90ms-width high pulse to notify micro processor. 2 pvd1 power output pin of ch1. to make ch1 stable, the power path from the pin pvd1 to its output capacitors must be as short ( 1mm is better) and wide as possible to reduce its parasitic inductance. the output capacitor must be ceramic capacitor ( 20 f). 3 lx1 switch node of ch1. 4 chg2 2nd charger status indicator (open drain output). 5 fb7 feedback input pin of ch7 in step-up mode or current regulator mode 6 pvd7 power output pin of ch7 in step-up or power input pin of ch7 in current regulator mode. 7 lx7 switch node of ch7 in step-up mode. lx7 initial voltage determine ch7 operation mode. 8 chg charger status indicator (open drain output). 9 vo6 power output pin of ch6. 10 pvd6 power input pin of ch6. 11 fb4 feedback input pin of ch4. 12 seq power sequence selection for ch1 to ch4. 13 lx4 switch node of ch4. 14 en enable pin of power converter unit. 15 pvd45 power input pin of ch4 and ch5. to avoid the crosstalk between ch4 and ch5, the power path from the pin pvd45 to its input capacitors must be as short ( 1mm is better) and wide as possible to reduce its parasitic inductance. the input capacitance must be 10 f with low esr. 16 lx5 switch node of ch5. 17 int interrupt indicator open drain output. if events of nobat, thr, eoc, battery temperature change (ts_meter), pgood, safe, vin dpm, or charge type detection finishing (chgrun) happen, the output int goes low and the int bit in i 2 c register bank 0x9 is set to be ?1?. after int bit is written to be ?0?, int goes high. 18 v o5/fb5 output voltage sense pin or feedback network input pin of ch5. the function is selected by i 2 c register. 19 pvd8 power input pin of ch8. 20 s da data signal pin of i 2 c interface. 21 s cl clock signal pin of i 2 c interface. 22 vo8 power output pin of ch8. 23 fb2 feedback input pin of ch2. 24 vo2 power output pin of ch2. 25 lx2b switch node b of ch2. 26 lx2a switch node a of ch2. 27 pvd2 power input pin of ch2.
RT5021 5 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? pin n o. pin name pin function 28 fb3 feedback input pin of ch3. 29 ts temperature sense input. the ts pin connects to a battery?s thermistor to determine if the battery is too hot or too cold to charge. if the battery?s temperature is out of range, charging is paused until it re-enters the valid range. ts also detects whether the battery (with ntc) is present or not. 30 vp power output pin of 3.3v buffer for battery temperature sensing. 31 lx3 switch node of ch3. 32 pvd3 power input pin of ch3. 33, 34 bat charger output for battery. 35, 36 sys power output for system. connect this pin to system with a minimum 10 f ceramic capacitor to gnd. 37 vin supply voltage input. 38 dp usb d+ input for charger type detection. 39 dn usb d- input for charger type detection. 40 vrtc rtc ldo power output pin. 41 (exposed pad) gnd exposed pad should be soldered to pcb and connected to gnd.
RT5021 6 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? function block diagram ch2 lv c-mode sync. step-up/down for 1a v ref + dvs vo2 lx2a pvd2 sys vp + - wake vrtc battery charger type detector dp dn vin register file output voltage of ch1 to ch6, ch8 ch7 dimming ratio and ovp threshold enable of ch5, ch6, ch7, ch8 pdm/pwm setting of ch1, ch2, ch3, ch4 charger type setting/status gnd vddi vp buffer with ntc type detector + - 3.3v sys chg_typ [2 : 0] chg_1det chg_2det chgrun ts comparators + - usus vseth vsetc iseth isetc isetl isetu timer [3 : 0] jeita sys bat li+ battery linear charge with appm thr eco pgood safe dpm ts_mester [2 : 0] ch9 rtc ldo with body diode control sys pvd1 vddi power plug-in wake up detector por bat vin enable control en por sequence detection & control seq sys i 2 c control interface (fast mode up to 400kb/s) scl sda interrupt handler sys thr eco pgood safe ts_meter [2 :0 ] no_bat dpm chgrun int ch6 low vin ldo sys + - v ref + dac pvd6 vo6 ch8 low vin ldo sys + - v ref + dac pvd8 vo8 lx7 + - pvd7 sys fb7 v ref + dac ch7 hv c-mode sync. step-up + current source + mode selector for 1 to 6wled body diode control sys lx1 ch1 c-mode step-up for 1a + - pvd1 sys v ref + dvs body diode control sys pvd1 lx2b fb2 ch3 c-mode step-down for 1.3a + - v ref + dvs lx3 pvd3 sys fb3 ch4 c-mode step-down for 1.3a + - v ref + dvs lx4 pvd45 sys fb4 ch5 c-mode step-down for 0.6a + - v ref + dvs lx5 pvd45 sys vo5/fb5 chg2 chg ench ts sys mask_dpm
RT5021 7 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? operation the RT5021 is an integrated power solution for digital still cameras and other small handheld devices. it includes six dc/dc converters, a wled driver, a rtc ldo, and a fully integrated single-cell li-ion battery charger. ch1 : step-up dc/dc converter ch1 is a step-up converter for motor driver power. the converter operates at pfm or pwm current mode which can be set by i 2 c interface. ch2 : step-up/down dc/dc converter ch2 is a step-up/down converter for i/o power. the converter operates at pfm or pwm current mode which can be set by i 2 c interface. ch3 : step-down dc/dc converter ch3 is a step-down converter for core power. the converter operates at pfm or pwm current mode which can be set by i 2 c interface. ch4 : step-down dc/dc converter ch4 is a step-down converter for memory power. the converter operates at pfm or pwm current mode which can be set by i 2 c interface. ch5 : step-down dc/dc converter ch5 is a step-down converter. the converter operates at pfm/pwm current mode. ch6 : generic ldo ch6 is a generic low voltage ldo for multiple purpose power. ch7 : wled driver ch7 is a wled driver that can operate in either current source mode or synchronous step-up mode which is determined by i 2 c interface control signal. ch8 : generic ldo ch8 is a generic low voltage ldo for multiple purpose power. ch9 : keep alive ldo and rtc ch9 is a ldo providing a 3.05v output for real time clock. charger unit a li-ion battery charger with automatic power path management is designed to operate in below modes. pre-charge mode when the output voltage is lower than 2.8v, the charging current will be reduced to a ratio of fast-charge current set by a8.iseta [3:0] to protect the battery life-time. fast-charge mode when the output voltage is higher than 3v, the charging current will be equal to the fast-charge current set by a8.iseta [3:0]. constant voltage mode when the output voltage is near 4.2v and the charging current falls below the termination current for a deglitch time of 25ms, the charger will be turned off and chg will go to high. re-charge mode when the chip is in charge termination mode, the charging current gradually goes down to zero. once the battery voltage drops to below 4.1v for 100ms, the charger will resume charging operation.
RT5021 8 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? recommended operating conditions (note 4) z supply input voltage, bat ----------------------------------------------------------------------------------------------- 1.8v to 5.5v z supply input voltage range, vin (a7.isetl = 1) ------------------------------------------------------------------- 4.4 v to 6v z supply input voltage range, vin (a7.isetl = 0) ------------------------------------------------------------------- 4.5 v to 6v z junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics (v sys = 3.3v, t a = 25 c, unless otherwise specified) power converter unit : parameter symbol test conditions min typ max unit supply voltage pmu startup voltage at sys v st for bootstrap 1.5 -- -- v sys operating voltage for pmu v sys 2.7 -- 5.5 v vddi over voltage protection (ovp) (hysteresis high) 5.82 6 6.18 v vddi ovp hysteresis (gap) -- ? 0.25 -- v vddi uvlo (hysteresis high) vddi uvlo takes effect once ch2 soft-start finish 2.2 2.4 2.6 v vddi uvlo hysteresis (gap) -- ? 0.3 -- v absolute maximum ratings (note 1) z supply voltage s, sys ---------------------------------------------------------------------------------------------------- ? 0.3v to 6v z supply input v oltage, vin ------------------------------------------------------------------------------------------------ ? 0.3v to 28v z switch node voltage, lx1, lx2, lx3, lx4, lx5 ---------------------------------------------------------------------- ? 0.3v to 6v z pvd7, lx7 -------------------------------------------------------------------------------------------------------------------- ? 0.3v to 25v z chg --------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 28v z chg2 -------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z other pins -------------------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z int, chg, chg2 continuous current ---------------------------------------------------------------------------------- 20ma z bat continuous current (total in two pins) ------------------------------------ ---------------------- ------------- --- 2.5a z power dissipation, p d @ t a = 25 c wqfn-40l 5x5 ------------------------------------------------------------------------------------------------------------- 3.64w z package thermal resistance (note 2) wqfn-40l 5x5, ja -------------------------------------------------------------------------------------------------------- 27.5 c/w wqfn-40l 5x5, jc ------------------------------------------------------------------------------------------------------- 6 c/w z junction temperature ------------------------------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 125 c z esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ------------------------------------------------------------------------------------------------------ 200v
RT5021 9 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit supply current shutdown supply current into bat (include i ddq of rtc ldo) i off-bat en = l, and pmu off, bat = 4.2v -- 10 20 a ch1 + ch2 + ch3 + ch4 supply current i q1234 non switching, en = 3.3v -- -- 2000 a ch5 supply current i q5 non switching, a2.en5 = 1 -- -- 500 a ch6 supply current i q6 a2.en6 = 1 -- -- 100 a ch7 in step-up mode supply current i q7b non s witching, a2.en7_dim7 [4:0] = 5?b11111 -- -- 500 a ch7 in current source mode supply current i q7c a2.en7_dim7 [4:0] = 5?b11111 pvd7 = 5v -- -- 400 a ch8 supply current i q8 a2.en8 = 1 -- -- 100 a oscillator ch1, 3, 4, 5 operation frequency f osc_1345 1800 2000 2200 khz ch2, 7 operation frequency f os c_2 7 ch7 in step-up mode 900 1000 1100 khz ch1 lv sync step-up output voltage accuracy at pvd1 target voltage defined at a4.vout1 [3:0] ? 1.5 -- 1.5 % minimum on time for psm -- 100 -- ns soft-start time pvd1 = 0 to 5v -- 4 -- ms maximum duty cycle (step-up) pvd1 < target defined in a4.vout1 [3:0] 80 83 86 % r ds(on)_p p-mosfet, pvd1 = 3.3v -- 200 300 m on resistance of mosfet r ds(on)_n n-mosfet, pvd1 = 3.3v -- 150 250 m current limitation (step-up) i lim_1 2.2 3 4 a over voltage protection at pvd1 5.82 6 6.18 v under voltage protection -1 at pvd1 -- sys ? 0.8 -- v under voltage protection -2 at pvd1 target voltage is defined in a4.vout1 [3:0] -- ta r g et x 0.5 -- v over load protection at pvd1 target voltage is defined in a4.vout1 [3:0] -- ta r g et ? 0.6 -- v off discharge current at pvd1 pvd1 = 5v, sys = 3.3v -- 20 -- ma discharge finishing threshold at pvd1 -- 0.6 -- v ch2 lv sync step-up/down feedback regulation voltage at fb2 a4.fb2 [2:0] = 3?b100 0.788 0.8 0.812 v soft-start time fb2 = 0 to 0.8v -- 4 -- ms lx2b -- 55 -- % maximum duty cycle lx2a -- -- 100 % lx2a ? gnd, n-mosfet pvd2 = 3.3v -- 200 300 m on resistance of mosfet r ds(on)_2a pvd2 ? lx 2a, p-mosfet pvd2 = 3.3v -- 150 250 m
RT5021 10 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit vo2 ? lx 2b, p-mosfet, vo2 = 3.3v -- 200 300 m on resistance of mosfet r ds(on)_2b lx2b ? gnd, n-mosfet vo2 = 3.3v -- 150 250 m current limitation i lim_2 both p-mosfet (pvd2 ? lx2a) and n-mosfet (lx2b ? gnd) 2 2.5 3 a over voltage protection at vo2 5.82 6 6.18 v under voltage protection at fb2 target voltage is the chosen one in a4.fb2 [2:0] -- 0.4 -- v over load protection at fb2 -- ta r ge t ? 0.1 -- v off discharge current at vo2 vo2 = 3.3v, sys = 3.3v -- 20 -- ma discharge finishing threshold at vo2 -- 0.1 -- v ch3 lv sync step-d own feedback regulation voltage at fb3 a5.fb3 [2:0] = 3?b100 0.788 0.8 0.812 v minimum on time for psm -- 50 -- ns maximum duty cycle fb3 = 0.75v -- -- 100 % soft-start time fb3 = 0 to 0.8v -- 4 -- ms r ds(on)_p p-mosfet, pvd3 = 3.3v -- 200 300 m on resistance of mosfet r ds(on)_n n-mosfet, pvd3 = 3.3v -- 150 250 m current limitation i lim_3 1.3 1.8 2.4 a under voltage protection at fb3 0.35 0.4 0.45 v over load protection at fb3 target voltage is the chosen one in a5.fb3 [2:0] -- ta r ge t ? 0.1 -- v off discharge current at lx3 lx3 = 1v, sys = 3.3v -- 20 -- ma discharge finishing threshold at fb3 -- 0.1 -- v ch4 lv sync step-d own feedback regulation voltage at fb4 a5.fb4 [2:0] = 3?b100 0.788 0.8 0.812 v minimum on time for psm -- 50 -- ns maximum duty cycle fb4 = 0.75v -- -- 100 % soft-start time fb4 = 0 to 0.8v -- 4 -- ms r ds(on)_p p-mosfet, pvd4 = 3.3v -- 300 400 m on resistance of mosfet r ds(on)_n n-mosfet, pvd4 = 3.3v -- 200 300 m current limitation i lim_4 1.3 1.8 2.4 a under voltage protection at fb4 0.35 0.4 0.45 v over load protection at fb4 target voltage is the chosen one in a5.fb4 [2:0] -- ta r g et ? 0.1 -- v off discharge current at lx4 lx4 = 1v, sys = 3.3v -- 20 -- ma discharge finishing threshold at fb4 -- 0.1 -- v
RT5021 11 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit ch5 lv sync step-d own target voltage defined at a6.vout5 [3:0] = 4?b1000 to 4?b1111 ? 1.5 -- 1.5 % output voltage accuracy at vo5 target voltage defined at a6.vout5 [3:0] = 4?b0001 to 4?b0111 ? 2 -- 2 % feedback regulation voltage at fb5 a6.vout5 [3:0 ] = 4?b0000 0.788 0.8 0.812 v maximum duty cycle -- -- 100 % soft-start time vo5 = 0v to target -- 4 -- ms r ds(on)_p p-mosfet, pvd5 = 3.3v -- 400 550 m on resistance of mosfet r ds(on)_n n-mosfet, pvd5 = 3. 3v -- 250 400 m current limitation i lim_5 1 1.5 2 a under voltage protection at vo5 -- target x 0.5 -- target voltage is the chosen one in a6.vout5 [3:0] = 0000 (fb5 = 0.8) -- target ? 0.1 -- target voltage is the chosen one in a6.vout5 [3:0] = 0001 to 0111 -- target ? 0.167 -- over load protection at vo5 target voltage is the chosen one in a6.vout5 [3:0] = 0111 to 1111 -- target ? 0.25 -- v off discharge current at vo5 vo5 = 1.8v, sys = 3.3v -- 30 -- ma discharge finishing threshold at vo5 -- 0.1 -- v ch6 ldo input voltage range (pvd6) 1.5 -- 5.5 v quiescent current into pvd6 pvd6 = 3.3v, i ou t = 0ma -- -- 75 a a6.vout6 [3:0] = 4?b1000 to 4?b1111 ? 1.5 -- 1.5 % regulation voltage accuracy at vo6 a6.vout6 [3:0] = 4?b0000 to 4?b0111 -2 -- 2 % drop out voltage (pvd6-vo6) i out = 300ma, vo6 = 1.3v -- -- 0.15 v psrr+ i out = 10ma, pvd6 = 3.3v at 1khz -- ? 60 -- db max output current (current limit) pvd6 = 1.5v, vo6 = 1.3v 300 450 600 ma off discharge current at vo6 sys = 3.3v -- -- 10 ma ch7 wled driver feedback regulation voltage at fb7 (both step-up and current) a2.en7_dim7 [4:0] = 5?b11111 0.237 0.25 0.263 v minimum on time for psm (step-up) -- 300 -- ns maximum duty cycle (step-up mode) fb7 = 0.15v 91 93 97 %
RT5021 12 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit r ds(on)_p p-mosfet, pvd7 = 10v -- 2 3 on resistance of mosfet r ds(on)_n n-mosfet, sys = 3.3v -- 0.9 1.1 current limitation (step-up mode) n-mosfet, sys = 3.3v 0.6 0.8 1 a a0.ovp7 = 0 15 16 17 v over voltage protection at pvd7 (step-up mode) a0.ovp7 = 1 24 25 26 v off discharge current at pvd7 (step-up mode) pvd7 = 10v, sys = 3.3v -- 20 -- ma discharge finishing threshold at pvd7 (step-up mode) -- sys ? 0.4 -- v ch8 ldo input voltage range (pvd8) 1.5 -- 5.5 v quiescent current into pvd8 i q_ pv d8 pvd8 = 3.3v, i out = 0ma -- -- 75 a a3.vout8 [3:0] = 4?b1000 to 4? b1111 ? 1.5 -- 1.5 % regulation voltage accuracy at vo8 a3.vout8 [3:0] = 4?b0000 to 4? b0111 ? 2 -- 2 % drop out voltage (pvd8-vo8) i ou t = 300ma, vo8 = 2.5v -- -- 0.2 v psrr+ i ou t = 10ma, pvd8 = 3.3v at 1k hz -- ? 60 -- db max output current (current limit) pvd8 = 3v, vo8 = 2.5v 300 450 600 ma off discharge current at vo8 sys = 3.3v -- -- 10 ma ch9 rtc ldo standby quiescent current bat = 4.2v -- 3 6 a lockout current into vrtc i lo-vrtc en = l, and pmu off, bat = 0v, vrtc = 3.05v, sys = 0v -- -- 1 a regulation voltage at vrtc i ou t = 0ma 3 3.05 3.1 v max output current (current limit) bat = 4.2v 60 130 200 ma i ou t = 50ma -- -- 1000 mv i ou t = 10ma -- -- 150 mv dropout voltage at (bat-vrtc) i ou t = 3ma -- -- 60 mv wake up detector wa ke impuls e hi gh duration t wakeup vin or bat plug in, vrtc = 3.05v 60 90 120 ms wake up high level v wake_h source current 0.5ma, vrtc = 3.05v -- vrtc ? 0.3v vrtc v wake up low level v wake_l sink current 0.5ma, vrtc = 3.05v 0 0.3 -- v wake up rising time t wake_r c load 100pf at wake pin, 10% to 90% of v rtc, vrtc = 3.05v -- -- 1 s bat wake up threshold voltage vrtc = 3.05v 3 3.1 3.2 v bat wake up threshold hysteresis gap vrtc = 3.05v -- ? 0.28 -- v
RT5021 13 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit vin wake up threshold voltage vrtc = 3.05v 3.55 3.75 4 v vin wake up threshold gap vrtc = 3.05v -- ? 0.24 -- v control en input high level threshold 1.3 -- -- v en input low level threshold -- -- 0.4 v en pull down current -- 1 3 a seq pull high threshold for power sequence #0 0.2 -- -- v seq pull down resistance for power sequence #1 bat = sys = 2.7v 25 40 64 k seq pull down resistance for power sequence #2 bat = sys = 2.7v 6.25 10 16 k seq pull down resistance for power sequence #3 bat = sys = 2.7v 1.56 2.5 4 k seq pull down resistance for power sequence #4 bat = sys = 2.7v -- 0.63 1 k seq pull low threshold for power sequence #4 -- -- 0.2 v seq pull down resistance for power sequence #5 bat = sys = 2.7v 100 160 -- k power sequence time gap from previous channel starting to next channel starting 9 10 11 ms protection protection fault delay -- 100 -- ms thermal shutdown t sd 125 155 -- c thermal shutdown hysteresis t sd -- 20 -- c
RT5021 14 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? (v in = 5v, v bat = 4v, t a = 25 c, unless otherwise specified) charger unit : parameter symbol test conditions min typ max unit supply input vin under voltage lockout threshold v uvlo v in = 0v to 4.5v 3.1 3.3 3.5 v vin under voltage lockout hysteresis vuvlo v in = 4.5v to 0v -- 240 -- mv i sys = i bat = 0ma, a7.ench = 0 (v bat > v regx ) -- 1 2 ma vin supply current i supply i sys = i bat = 0ma, a7.ench = 1 (v bat > v regx ) -- 0.8 1.5 ma vin suspend current i usus v in = 5v, a7.usus = 1 -- 195 300 a vin ? bat vos rising v os_h -- 200 300 mv vin ? bat vos falling v os_l 10 50 -- mv voltage regulation system regulation voltage v sys i sys = 800ma 4.9 5 5.1 v battery regulation voltage v reg1 0 to 85c, loading = 20ma, when a9. vseth = 1 and a9.vsetc = 1 4.16 4.2 4.23 v battery regulation voltage v reg2 0 to 85c, loading = 20ma, when a9. vseth = 0 and a9. vsetc = 0 4.01 4.05 4.08 v appm regulation voltage v appm 4.05 4.15 4.25 v dpm regulation voltage v dpm 4.25 4.35 4.45 v vin to vsys mosfet ron r ds(on) i vin = 1000ma -- 0.2 0.35 bat to vsys mosfet ron r ds(on) v bat = 4.2v, i sys = 1a -- 0.05 0.1 re-charge threshold v regchg battery regulation - recharge level 60 100 140 mv current regulation charge current setting range i chg 100 -- 1200 ma charge current accuracy1 i chg1 v bat = 4v, a8.iseta [3 : 0] = 4?b0101 570 600 630 ma charge current accuracy2 i chg2 vbat = 3.8v, a8.iseta [3 : 0] = 4?b0010 285 300 315 ma a7.isetl = 1, a7.isetu = 1 (1.5a mode) 1.5 1.8 2.1 a a7.isetl = 1, a7.isetu = 0 (1a mode) 0.85 0.925 1.0 a a7.isetl = 0, a7.isetu = 1 (500ma mode) 450 475 500 ma vin current limit i lim_vin a7.isetl = 0, a7.isetu = 0 (100ma mode) 80 90 100 ma pre-charge bat pre-charge threshold v prech bat falling 2.7 2.8 2.9 v bat pre-charge threshold hysteresis v prech -- 200 -- mv pre-charge current i chg_pre v bat = 2v 5 10 15 %
RT5021 15 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit charge termination detection termination current ratio to fast charge (except usb 100 mode) i term a7.isetl = 0, a7.isetu = 1 or a7.isetl = 1, a7.isetu = x 5 10 15 % termination current ratio to fast charge (usb100 mode) i term2 a7.isetl = 0, a7.isetu = 0 -- 3.3 -- % login input/output chg pull down voltage v chg i chg = 5ma -- 200 -- mv chg2 pull down voltage v chg2 i chg2 = 5ma -- 200 -- mv int pull down voltage v int i int = 5ma -- 200 -- mv protection thermal regulation point t reg -- 125 -- c thermal shutdown temperature t sd -- 155 -- c thermal shutdown hysteresis t sd -- 20 -- c over voltage protection v ovp v in rising 6.25 6.5 6.75 v over voltage protection hysteresis v ov p v in = 7v to 5v, vovp ? vovp -- 100 -- mv output short circuit detection threshold v short vbat ? vsys -- 300 -- mv battery installation detection threshold at ts en = h (pmu enabled), report at a10. nobat bit -- 90 -- % of vp time input over voltage blanking time t ov p -- 50 -- s pre-charge to fast-charge deglitch time t pf -- 25 -- ms fast-charge to pre-charge deglitch time t fp -- 25 -- ms termination deglitch time t termi -- 25 -- ms recharge deglitch time t rechg -- 100 -- ms input power loss to sys ldo turn-off delay ti me t no_in -- 25 -- ms pack temperature fault detection deglitch time t ts -- 25 -- ms short circuit deglitch time t short -- 250 -- s short circuit recovery time t short-r -- 64 -- ms other vp regulation voltage v vp v sys = 4.2v 3.234 3.3 3.366 v vp load regulation v vp vp source out 2ma -- -- ? 0.1 v
RT5021 16 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? parameter symbol test conditions min typ max unit vp under voltage lockout threshold falling threshold -- 0.8 -- v ts battery detect threshold v ts 2.75 2.85 2.95 v ntc temperature sense v too_cold ntc = 100k 73 74 75 % of v p low temperature trip point (0c) v too_cold ntc = 10k 59 60 61 % of v p v cold ntc = 100k 63 64 65 % of v p low temperature trip point (10c) for jeita v cold ntc = 10k 51 52 53 % of v p v hot ntc = 100k 34 35 36 % of v p high temperature trip point (45c) for jeita v hot ntc = 10k 31 32 33 % of v p v too_hot ntc = 100k , a8.tsht [1:0] = 2?b00 27 28 29 % of v p high temperature trip point (60c) v too_hot ntc = 10k , a8.tsht [1:0] = 2?b00 27 28 29 % of v p high temperature trip point hysteresis for jeita -- 1 -- % of v p charger detection vdp_src voltage vdp_src with idat_src = 0 to 200 a 0.5 -- 0.7 v vdat_ref voltage vdat_ref 0.25 -- 0.4 v vlgc voltage vlgc 0.8 -- 2.0 v idp_src current idp_src 6.6 -- 11 a d+ and d- sink current icd+_sink icd-_sink 50 -- 150 a d- pull down resistor rd-_dwn 14.25 -- 24.8 k data contact detect debounce t dcd_dbnc 20 30 40 ms dcd time out tdcd_to 300 -- 900 ms vdat_src on time tdp_src_on 100 -- 200 ms
RT5021 17 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit i 2 c sda, sclk input high level threshold 1.4 -- -- v sda, sclk input low level threshold - -- 0.6 v sclk clock rate f scl -- -- 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd,sta 0.6 -- -- s low period of the scl clock t low 1.3 -- -- s high period of the scl clock t high 0.6 -- -- s set-up time for a repeated start condition t su ,sta 0.6 -- -- s data hold time t hd,dat 0 -- 0.9 s data set-up time t su ,dat 100 -- -- ns set-up time for stop condition t su ,sto 0.6 -- -- s bus free time between a stop and start condition t bu f 1.3 -- -- s rise time of both sda and scl signals t r 20 -- 300 ns fall time of both sda and scl signals t f 20 -- 300 ns sda and scl output low sink current i ol sda or scl voltage = 0.4v 2 -- -- ma (v sys = 3.3v, t a = 25 c, unless otherwise specified)
RT5021 18 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? typical application circuit figure 1. typical application circuit for dsc with 6-led backlight note : to make ch1 stable, c27 must be close to pvd1. to make ch4 and ch5 stable, c28 must be close to pvd45. RT5021 25 lx2b pvd3 32 ts 29 pvd1 lx2a 26 pvd2 27 vo2 24 fb2 23 fb3 28 gnd 41 (exposed pad) 4 17 sys 35, 36 38 dn 39 dp scl 21 14 en wake 1 22 pvd8 19 vo8 vrtc 40 6 pvd7 pvd6 vo6 10 9 2.2h 5 fb7 vp 30 vin 37 2 2.2f v bus bat 33, 34 1f + ntc 10f x 2 motor 5v lx1 3 2.2h 4.7f v sys 10f v sys 10f x 2 22pf 300k 96k 4.7f v sys i/o 3.3v 2.2h 10f core 1v lx3 31 232k pvd45 15 10f v sys 931k fb4 11 2.2h 10f ddriii 1.5v lx4 13 327k 374k lx5 16 vo5/fb5 18 1.8v 2.2h v sys d+ d- to usb chg2 v sys charge 2 indicator 8 v sys charge indicator chg 0.1f super cap vrtc wake up signal to p 1f 3.3v 1f 2.8v enable 12 seq v sys sda 20 i 2 c bus int 3.3v interrupt to p 1f 10 1f 1.5v 1f 1.3v c14 c2 r1 r2 r ntc c3 l1 c4 c5 l2 c6 c7 r3 r4 c8 l3 r5 r6 c9 c10 l4 r7 r8 c11 l5 10f c12 r11 c1 r12 c17 c18 c19 r13 1k r14 1k r15 c21 d2 r16 c23 c24 7 lx7 backlight 1f c22 v sys 10h l7 d3 d4 d5 d6 d7 10f 10k 10k v sys 10k 68pf c25 47pf c26 0.1f c27 0.1f c28
RT5021 19 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? figure 2. typical application circuit for dsc with one led backlight note : to make ch1 stable, c27 must be close to pvd1. to make ch4 and ch5 stable, c28 must be close to pvd45. RT5021 25 lx2b pvd3 32 ts 29 pvd1 lx2a 26 pvd2 27 vo2 24 fb2 23 fb3 28 gnd 41 (exposed pad) 4 17 sys 35, 36 38 dn 39 dp scl 21 14 en wake 1 22 pvd8 19 vo8 vrtc 40 6 pvd7 pvd6 vo6 10 9 2.2h 7 lx7 5 fb7 vp 30 vin 37 2 2.2f v bus bat 33, 34 1f + ntc 10f x 2 motor 5v lx1 3 2.2h 4.7f v sys 10f v sys 10f x 2 22pf 300k 96k 4.7f v sys i/o 3.3v 2.2h 10f core 1v lx3 31 232k pvd45 15 10f v sys 931k fb4 11 2.2h 10f ddriii 1.5v lx4 13 327k 374k lx5 16 vo5/fb5 18 33pf 470k 374k 1.8v 2.2h v sys d+ d- to usb chg2 v sys charge 2 indicator 8 v sys charge indicator chg 0.1f super cap vrtc wake up signal to p 1f 3.3v 1f 2.8v enable 12 seq v sys sda 20 i 2 c bus int 3.3v interrupt to p 1f motor 4.3v 10 backlight 1f 1.5v 1f 1.3v c14 c2 r1 r2 r ntc c3 l1 c4 c5 l2 c6 c7 r3 r4 c8 l3 r5 r6 c9 c10 l4 r7 r8 c11 l5 c13 10f c12 r9 r10 r11 c1 r12 c17 c18 c19 r13 1k r14 1k r15 c20 d1 r16 c23 c24 10f 10k 10k v sys 10k 68pf c25 47pf c26 0.1f c27 0.1f c28
RT5021 20 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? typical operating characteristics v in = 5v, unless otherwise specified. ch2 step-up/down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 3.3v, l = 2.2 h, c out = 10 f x 2 v bat = 2.7v v bat = 3v v bat = 3.6v v bat = 4.2v v bat = 5v ch3 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1v, l = 2.2 h, c out = 10 f v bat = 2.7v v bat = 3.3v v bat = 3.9v v bat = 4.2v v bat = 5v ch4 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1.5v, l = 2.2 h, c out = 10 f v bat = 2.7v v bat = 3.3v v bat = 3.9v v bat = 4.2v v bat = 5v ch7 efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 input voltage (v) efficiency (%) l = 10 h, c out = 1 f, i out = 6wleds ch1 step-up efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 5v, l = 2.2 h, c out = 10 f x 2 v bat = 4.5v v bat = 4.2v v bat = 3.9v v bat = 3.6v v bat = 3.3v v bat = 2.7v ch5 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1.8v, l = 2.2 h, c out = 10 f v bat = 2.7v v bat = 3.3v v bat = 3.9v v bat = 4.2v v bat = 5v
RT5021 21 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ch5 step-down output voltage vs. output current 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1.84 0 200 400 600 800 1000 output current (ma) output voltage (v) v out = 1.8v v sys = 2.7v v sys = 3.4v v sys = 4.2v v sys = 5v ch6 ldo output voltage vs. output current 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 0 50 100 150 200 250 300 350 400 output current (ma) output voltage (v) v out = 1.3v pvd6 = 1.5v pvd6 = 3.3v ch3 step-down output voltage vs. output current 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 200 400 600 800 1000 output current (ma) output voltage (v) v out = 1v v sys = 2.7v v sys = 3.4v v sys = 4.2v v sys = 5v ch4 step-down output voltage vs. output current 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 1.525 0 200 400 600 800 1000 output current (ma) output voltage (v) v out = 1.5v v sys = 2.7v v sys = 3.4v v sys = 4.2v v sys = 5v ch2 step-up/down output voltage vs. output current 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 0 100 200 300 400 500 600 output current (ma) output voltage (v) v out = 3.3v v sys = 2.7v v sys = 3.4v v sys = 4.2v v sys = 5v ch1 step-up output voltage vs. output current 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0 200 400 600 800 1000 output current (ma) output voltage (v) v out = 5v v sys = 2.7v v sys = 3.4v v sys = 4.2v v sys = 5v
RT5021 22 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? v bat = 3.7v, v out = 5v, i out = 400ma, l = 2.2 h, c out = 10 f x 2 time (500ns/div) ch1 output voltage ripple v out_ch1_ac (5mv/div) lx1 (5v/div) time (500ns/div) ch3 output voltage ripple v bat = 3.7v, v out = 1v, i out = 400ma, l = 2.2 h, c out = 10 f v out_ch3_ac (5mv/div) lx3 (5v/div) time (500ns/div) ch5 output voltage ripple v bat = 3.7v, v out = 1.8v, i out = 400ma, l = 2.2 h, c out = 10 f v out_ch5_ac (5mv/div) lx5 (5v/div) time (500ns/div) ch4 output voltage ripple v bat = 3.7v, v out = 1.5v, i out = 400ma, l = 2.2 h, c out = 10 f v out_ch4_ac (5mv/div) lx4 (5v/div) ch8 ldo output voltage vs. output current 2.400 2.425 2.450 2.475 2.500 2.525 2.550 2.575 2.600 0 50 100 150 200 250 300 350 400 450 500 output current (ma) output voltage (v) v out = 1.3v pvd8 = 2.7v pvd8 = 3.3v time (500ns/div) ch2 output voltage ripple v bat = 3.7v, v out = 3.3v, i out = 400ma, l = 2.2 h, c out = 10 f x 2 v out_ch2_ac (5mv/div) lx2 (5v/div)
RT5021 23 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? time (250 s/div) ch1 load transient response v bat = 3.7v, v out = 5v, i out = 0 to 300ma, l = 2.2 h, c out = 10 f x 2 v out_ch1_ac (100mv/div) i out (200ma/div) time (250 s/div) ch5 load transient response v bat = 3.7v, v out = 1.8v, i out = 100ma to 300ma, l = 2.2 h, c out = 10 f v out_ch5_ac (50mv/div) i out (200ma/div) time (250 s/div) ch6 load transient response v bat = 3.7v, v out = 1.3v, i out = 100ma to 300ma, c out = 1 f v out_ch6_ac (50mv/div) i out (200ma/div) time (250 s/div) ch4 load transient response v bat = 3.7v, v out = 1.5v, i out = 100ma to 300ma, l = 2.2 h, c out = 10 f v out_ch4_ac (50mv/div) i out (200ma/div) time (250 s/div) ch3 load transient response v bat = 3.7v, v out = 1v, i out = 100ma to 300ma, l = 2.2 h, c out = 10 f v out_ch3_ac (20mv/div) i out (200ma/div) time (250 s/div) ch2 load transient response i out = 100ma to 300ma, l = 2.2 h, c out = 10 f x 2 v out_ch2_ac (50mv/div) i out (200ma/div) v bat = 3.7v, v out = 3.3v,
RT5021 24 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? time (250 s/div) ch8 load transient response v bat = 3.7v, v out = 2.5v, i out = 100ma to 300ma, c out = 1 f v out_ch8_ac (50mv/div) i out (200ma/div) power on sequence 0 v out_2 (2v/div) v out_3 (1v/div) v out_4 (1v/div) time (5ms/div) v bat = 3.7v time (500 s/div) power off sequence 0 v bat = 3.7v v out_2 (2v/div) v out_3 (1v/div) v out_4 (1v/div) power on sequence 1 v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v bat = 3.7v time (5ms/div) v out_1 (5v/div) time (1ms/div) power off sequence 1 v bat = 3.7v v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) power on sequence 2 v bat = 3.7v time (5ms/div) v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div)
RT5021 25 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? power on sequence 5 v bat = 3.7v time (5ms/div) v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) time (5ms/div) power off sequence 4 v bat = 3.7v v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) time (1ms/div) power off sequence 3 v bat = 3.7v v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) power on sequence 4 v bat = 3.7v time (5ms/div) v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) time (1ms/div) power off sequence 2 v bat = 3.7v v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) power on sequence 3 v bat = 3.7v time (5ms/div) v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div)
RT5021 26 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? time (50ms/div) battery with ntc resistor plug-in v in (5v/div) v ts (5v/div) v bat (5v/div) i bat (500ma/div) v bat = real battery, 500ma mode time (500ms/div) v in over voltage protection v in (10v/div) v sys (5v/div) v bat (5v/div) i bat (2a/div) v in = 5v to 15v, v bat = real battery, 1.5a mode time (500ms/div) v ts on/off v ts (2v/div) i bat (500ma/div) v bat (5v/div) control v ts by function generator v bat = real battery, 500ma mode, v chg1 (5v/div) time (10ms/div) v in removal v sys (5v/div) v bat (5v/div) i bat (2a/div) v in (5v/div) r sys = 10 , 1.5a mode v bat = real battery, time (1ms/div) power off sequence 5 v bat = 3.7v v out_2 (5v/div) v out_3 (1v/div) v out_4 (1v/div) v out_1 (5v/div) time (50ms/div) charge on/off control by i 2 c v bat = real battery, 500ma mode v sda (5v/div) i bat (500ma/div) v bat (5v/div) v chg (5v/div)
RT5021 27 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? time (50ms/div) with battery without ntc resistor v in (5v/div) v ts (5v/div) v bat (5v/div) i bat (500ma/div) v bat = real battery, 500ma mode time (250ms/div) battery with ntc resistor plug-out v in (5v/div) v ts (5v/div) v bat (5v/div) i bat (500ma/div) v bat = real battery, 500ma mode time (500ms/div) v in exist then negative battery and plug-out v in (5v/div) v sys (10v/div) v bat (5v/div) i in (100ma/div) v bat = real battery, r sys = 50 , 100ma mode time (50ms/div) with ntc resistor without battery v in (5v/div) v ts (5v/div) v bat (5v/div) i bat (500ma/div) v bat = real battery, 500ma mode time (25ms/div) the temperature of battery status v bat (2v/div) v ts (2v/div) normal -> too cold (voltage) v bat = real battery, 1.5a mode jeita = 0, vseth = 1, vsetc = 1, or jeita = 0, vseth = 0, vsetc = 1, or jeita = 1, vseth = 1, vsetc = x time (50ms/div) negative battery then v in plug-in v in (5v/div) v sys (10v/div) v bat (5v/div) i in (500ma/div) r sys = 10 , 500ma mode v bat = real battery,
RT5021 28 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? time (25ms/div) the temperature of battery status i bat (1a/div) v ts (2v/div) normal -> too hot (current) v bat = real battery, 1.5a mode jeita = 1, iseth = 1, isetc = x jeita = 0, iseth = 1, isetc = 0, or jeita = 0, iseth = 1, isetc = 1, or time (25ms/div) the temperature of battery status v bat (2v/div) v ts (2v/div) normal -> hot -> too hot (voltage) v bat = real battery, 1.5a mode jeita = 0, vseth = 0, vsetc = 0, or jeita = 0, vseth = 0, vsetc = 1 time (25ms/div) the temperature of battery status i bat (1a/div) v ts (2v/div) normal -> cold -> too cold (current) v bat = real battery, 1.5a mode jeita = 0, iseth = 0, isetc = 0, or jeita = 0, iseth = 1, isetc = 0 time (25ms/div) the temperature of battery status v bat (2v/div) v ts (2v/div) normal -> cold -> too cold (voltage) v bat = real battery, 1.5a mode jeita = 0, vseth = 0, vsetc = 0, or jeita = 0, vseth = 1, vsetc = 0 time (25ms/div) the temperature of battery status i bat (1a/div) v ts (2v/div) normal -> too cold (current) v bat = real battery, 1.5a mode jeita = 0, iseth = 1, isetc = 1, or jeita = 0, iseth = 0, isetc = 1, or jeita = 1, iseth = 1, isetc = x time (25ms/div) the temperature of battery status v bat (2v/div) v ts (2v/div) normal -> too hot (voltage) v bat = real battery, 1.5a mode jeita = 1, vseth = 1, vsetc = x jeita = 0, vseth = 1, vsetc = 0, or jeita = 0, vseth = 1, vsetc = 1, or
RT5021 29 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? v in - v sys dropout voltage vs. temperature 200 225 250 275 300 325 350 375 400 425 450 -50 -25 0 25 50 75 100 125 temperature (c) v in - v sys dropout voltage (mv) v bat - v sys dropout voltage vs. temperature 50 55 60 65 70 75 80 85 90 95 100 -50 -25 0 25 50 75 100 125 temperature (c) v bat - v sys dropout voltage (mv) i sys = 1a v bat = 3.7v, i sys = 1a, usus = h time (25ms/div) the temperature of battery status i bat (1a/div) v ts (2v/div) normal -> hot -> too hot (current) jeita = 0, iseth = 0, isetc = 0, or jeita = 0, iseth = 0, isetc = 1, time (1ms/div) i in v sys v in v bat = real battery, 1.5a mode i sys = 0a to 2a appm v bat i sys i bat (1v/div) / (1a/div) system regulation voltage vs. temperature 4.85 4.87 4.89 4.91 4.93 4.95 4.97 4.99 5.01 5.03 5.05 -50 -25 0 25 50 75 100 125 temperature (c) system regulation voltage (v) 1 i sys = 0.5a ovp threshold voltage vs. temperature 6.32 6.34 6.36 6.38 6.40 6.42 6.44 6.46 6.48 6.50 6.52 -50 -25 0 25 50 75 100 125 temperature (c) ovp voltage (v) rising falling
RT5021 30 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? fast-charge current vs. battery voltage 400 450 500 550 600 650 700 750 800 3 3.2 3.4 3.6 3.8 4 4.2 battery voltage (v) fast-charge current (ma ) pre-charge current vs. battery voltage 0 10 20 30 40 50 60 70 80 2 2.2 2.4 2.6 2.8 3 battery voltage (v) pre-charge current (ma ) battery regulation voltage vs. temperature 4.10 4.12 4.14 4.16 4.18 4.20 4.22 4.24 4.26 -50 -25 0 25 50 75 100 125 temperature (c) battery voltage (v) v bat = real battery i chg thermal regulation vs. temperature 0 50 100 150 200 250 300 350 400 450 500 -50 -25 0 25 50 75 100 125 temperature (c) i chg thermal regulation (ma ) v bat = real battery
RT5021 31 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? application information power converter unit the RT5021 is an integrated power solution for digital still cameras and other small handheld devices. it includes six dc/ dc converters, a wled driver, two low output ldo, a rtc ldo, and a fully integrated single-cell li-ion battery charger that is ideal for portable applications. ch1 : synchronous step-up dc/dc converter the synchronous step-up dc/dc converter can be operated in either pfm or sync-pwm mode by setting i 2 c. it includes internal power mosfets, compensation network and feedback resistors. the p-mosfet can be controlled to disconnect output loading. it is suitable for providing power to the motor. the output voltage of ch1 can be adjusted by the i 2 c interface in the range of 3.6v to 5.5v. ch1 regulation voltage can be selected by i 2 c interface. the default voltage is 5v. code voltage code voltage code voltage code voltage 0000 3.6v 0001 3.7v 0010 3.8v 0011 3.9v 0100 4v 0101 4.5v 0110 4.6v 0111 4.7v 1000 4.8v 1001 4.9v 1010 5v 1011 5.1v vout1 [3:0] 1100 5.2v 1101 5.3v 1110 5.4v 1111 5.5v ch2 : synchronous step-up/down (buck-boost) dc/dc converter the synchronous step-up/down (buck-boost) dc/dc converter can be operated in either pfm or sync-pwm mode by setting i 2 c. it includes internal power mosfets, compensation network and feedback resistors. this channel supplies the power for i/o. the fb voltage of ch2 can be adjusted by the i 2 c interface in the range of 0.72v to 0.86v. fb2 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb2 [2:0] 111 0.86v 1.935v 1.075v 3.5475v
RT5021 32 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ch3 to ch4 : step-down synchronous dc/ dc converter the step-down synchronous dc/ dc converters include internal power mosfets and compensation network. it support pfm or sync-pwm mode by setting i 2 c. these channels supply the power for core and dram. they can be operated at 100% maximum duty cycle to extend battery operating voltage range. when the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. the fb voltage of ch3 and ch4 can be adjusted by the i 2 c interface in the range of 0.72v to 0.86v. fb3 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb3 [2:0] 111 0.86v 1.935v 1.075v 3.5475v fb4 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb4 [2:0] 111 0.86v 1.935v 1.075v 3.5475v if ch3/ch4 input voltage (pvd3/pvd45) is higher than 4.2v and the output voltage is lower than 1.5v, a feed forward capacitor can be added improve the transient response. the capacitance can be estimated by the following equation. for example, when r1 is 470k , the available feed-forward capacitor is 33pf. vout r1 r2 c ff fb ? 6 ff 15.5 10 c = r1
RT5021 33 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ch5 : step-down synchronous dc/ dc converter the step-down synchronous dc/ dc converter includes internal power mosfets and compensation network. they can be operated at 100% maximum duty cycle to extend battery operating voltage range. when the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. the output voltage can be selected as the following list or set by external feedback network. ch5 regulation voltage can be selected by i 2 c interface. the default voltage is 1.8v. code voltage code voltage code voltage code voltage 0000 ref 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.3v 1100 2.5v 1101 2.6v 1110 2.7v 1111 2.8v vout5 [3:0] note : vout5 [3:0] = 0000 (ref) means using external feedback network and fb5 regulation target is 0.8v 1.5% ch6 : low voltage ldo ch6 is a low voltage ldo and its output voltage is controlled by i 2 c interface. this supplies the multiple purpose power. the output voltage of ch6 can be adjusted by the i 2 c interface in the range of 1.1v to 3.3v. ch6 regulation voltage can be selected by i 2 c interface. the default voltage is 1.3v. code voltage code voltage code voltage code voltage 0000 switch 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.5v vout6 [3:0] 1100 2.8v 1101 3.1v 1110 3.2v 1111 3.3v ch7 : current source/step-up wled driver the wled drivers operating in either current source mode or synchronous step-up mode include internal power mosfet and compensation network. the operation mode is determined by setting i 2 c. the p-mosfet in step-up mode can be controlled to disconnect the output loading. when ch7 works in current source mode, it likes a ldo and regulates the current by fb7 voltage. the led current is defined by the fb7 voltage as well as the external resistor between fb7 and gnd. the fb7 regulation voltage can be set in 31 steps from 8mv to 250mv. if ch7 works in synchronous step-up mode, it can support an output voltage up to 15v or 21v controlled by i 2 c interface. the led current is also set via an external resistor and fb7 regulation voltage. the wled current can be set by the following equation : iled (ma) = [250mv / r ( )] x en7_dim7 [4:0] / 31 where r is the current sense resistor from fb7 to gnd and en7_dim7 [4:0] / 31 ratio refers to the i 2 c control register file.
RT5021 34 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ch8 : low voltage ldo ch8 is a low voltage ldo and its output voltage is controlled by i 2 c interface. it supplies for multiple purpose power. the output voltage of ch8 can be adjusted by the i 2 c interface in the range of 1.1v to 3.3v. ch8 regulation voltage can be selected by i 2 c interface. the default voltage is 2.8v. code voltage code voltage code voltage code voltage 0000 switch 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.5v vout8 [3:0] 1100 2.8v 1101 3.1v 1110 3.2v 1111 3.3v rtc_ldo : accuracy 3.05v ldo output. the RT5021 provides a 3.05v output ldo for real-time clock. the ldo features low quiescent current (3 a), reverse leakage prevention from output node and high output voltage accuracy. this ldo is always on, even when the system is shut down. for better stability, it is recommended to connect a 0.1 f capacitor to the rtcpwr pin. the rtc ldo includes pass transistor body diode control to avoid the rtcpwr node from back-charging into the input node vddi. switching frequency the converters of ch1, ch3, ch4 and ch5 operate in pwm mode with 2mhz switching frequency. the converters of ch2 and ch7 operates in pwm mode with 1mhz switching frequency. power on/off sequence and deglitch function for ch1 to ch4 seq pull down resistance r seq defines power on/off sequence. r seq (k ) range seq# min typ max seq #0 short to power (>0.2v) seq #1 25 40 64 seq #2 6.25 10 16 seq #3 1.56 2.5 4 seq #4 -- 0.63 1 seq #5 100 160 -- seq # 0 : ch2 ch3 ch4 (ch1 is decided by register a4 bit3.) seq # 1 : ch1 ch3 ch2 ch4 seq # 2 : ch1 ch3 ch4 ch2 seq # 3 : ch1 ch2 ch4 ch3 seq # 4 : ch1 ch4 ch3 ch2 seq # 5 : ch1 ch4 ch2 ch3 floating = resistance greater than 160k = seq#5 the power on sequence of ch1 to ch4 is shown below : (using seq #3 : ch1 ch2 ch4 ch3 to explain) when en1234 goes high, ch1 will be turned on first then ch2 will be turned on after ch1 turn on for 10msec, likewise, ch4 will be turned on after ch2 turns on for 10msec. finally, ch3 is turned on after ch4 turns on for 10msec. the soft- start time is 4msec for each channel. the power off sequence of ch1 to ch4 is : when en1234 goes low, ch3 will turn off first and internally discharge output via lx3 pin. when fb3 < 0.1v, ch4 will turn off and also internally discharge output via the lx4 pin. when fb4 < 0.1v, ch2 will turn off and internally discharge output via the lx2 pin. likewise, when fb2 < 0.1v, ch1 will turn off and discharge output. after fb1 < 0.1v, ch1 to ch4 shutdown sequence is completed.
RT5021 35 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? during on sequence period, en going low would not take effect. after the sequence finish, en state would be re-checked and decide to keep on or start off sequence. during off sequence period, en going high would not take effect. after the sequence finish, en state would be re-checked and decide to keep off or start on sequence. external en vout3 (1.1v) seq_ready vref/iref /osc/por vout4 (1.5v) latch seq detection result por and enable vref/iref/osc seq detection power on sequence power off sequence t r 4ms t d 10ms t d 10ms vout1 (5v) t r 4ms vout6 enabled in i 2 c vout2 (3.3v) vout5 each enabled in i 2 c t r 4ms t d 10ms por and enable vref/iref/osc seq detection power on sequence external en vout3 (1.1v) seq_ready vref/iref/ osc/por vout4 (1.5v) latch seq detection result por and enable vref/iref/osc seq detection power on sequence power off sequence would finish and then re-start t r 4ms t d 10ms t d 10ms vout1 (5v) t r 4ms vout2 (3.3v) last channel discharge finish and then reset seq detection result and issue next time to re-detect seq latch seq detection result en going low take no effect during on sequence period. t r 4ms t d 10ms t r 4ms t d 10ms t r 4ms t d 10ms t r 4ms t d 10ms
RT5021 36 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? vddm bootstrap to support bootstrap function, the RT5021 provides a power selection circuit which selects the maximum voltage between sys and pvd1 to support the power requirement at node vddi. the RT5021 includes uvlo circuits to monitor vddi and sys voltage status. figure 3 charger unit the RT5021 includes a li-ion battery charger with automatic power path management. the charger is designed to operate in below modes : ` pre-charge mode when the output voltage is lower than 2.8v, the charging current will be reduced to a ratio of the fast-charge current set by a8.iseta [3:0] to protect the battery life-time. the timing diagram is showed in figure 3. ` fast-charge mode when the output voltage is higher than 3v, the charging current will be equal to the fast-charge current set by a8.iseta [3:0] shown as figure 3. ` constant voltage mode when the output voltage is near 4.2v and the charging current falls below the termination current for a deglitch time of 25ms, the charger will be disabled and chg will go high. the timing diagram is showed in figure 3. ` re-charge mode when the chip is in charge termination mode, the charging current gradually goes down to zero. once the battery voltage drops to below 4.1v for a deglitch time of 100ms, the charger will resume charging shown as figure 3. sys pvd1 vddi = max (sys, pvd1) 4.16 to 4.2 to 4.23v ? 40 c to 85 c battery voltage charging current v prech v rech i term2 if isetl = 0, isetu = 0 i termi = 3.3% x i chg_fast if isetl = 1, isetu = 1 isetl = 0, isetu = x i termi = 10% x i chg_fast time i chg_pre = 10% x i chg_fast
RT5021 37 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? int vs. fault/status timing diagram interrupt vs. events (i 2 c status bits) when pmu turns on with event condition during pmu on int assert (turn to low) no event (0) event has occurred (1) event appear (0 1) event disappear (1 0) pgood no yes yes yes nobat no yes yes yes ts_meter [2:0] = 000 (event may be cold or hot, vp uvlo, nobat) no yes yes yes eoc no yes yes yes thr no yes yes yes safe no yes yes yes dpm no yes yes yes chgrun no no no yes thr eoc pgood a9.int bit is written to "0" ts_meter [2:0] nobat chgrun dpm safe int when the a9.int bit is written to "0", the int will be set to high. when mask_dpm = 1 and dp m event change, the int would not be asserted. (mask_dpm = 0) interrupt indicator the RT5021 provides an interrupt indicator output pin (int). int is an open drain output which is controlled by a9.int bit. when the pgood, ts_meter [2:0], eoc, thr, safe, nobat, chgrun, dpm status bits toggle, the a9.int bit will be set to high. in order to reset the interrupt status, a ? 0 ? must be written to the a9.int bit or power on the pmu again. the timing diagram is shown below :
RT5021 38 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? battery installation detection RT5021 also detects ts voltage to monitor the battery status. if pmu is enabled but ts voltage > 90% of vp node voltage, RT5021 sets the bit nobat = 1 an i 2 c register a10.nobat and sets a9.int bit to ? 1 ? . 1 no battery installed (ts > 90% of vp) nobat 0 bat installed 0 vin < vuvlo 0 vuvlo < vin < vbat + vos_l 1 vbat + vos_h < vin < vovp pgood 0 v in > vovp vin power good status end_of_charge (eoc) status the bit eoc in i 2 c register a10.eoc can show the eoc status. if eoc = 1, the charger is in eoc state and a9.int bit is set to ? 1 ? 1 charging done or recharging after termination eoc 0 during charging wake-up detector wake-up detector detects vin or bat plug-in events. once bat plugs in or vin plugs in for a 19msec deglitch time, the wake pin will provide a 90ms width high pulse. the timing diagram shows as below. when pmu is enabled, wake up impulse would be masked off. wake impulse width 90ms can not be cut by en = h 90ms 90ms wake en no wake impulse bat plug in bat exists vin plug in bat/vin plug in vin 90ms 90ms 3.1v bat bat > 3.1v bat > 3.1v wake up vin > 3.75v when bat > 3.1v wake up 3.1v wake 20ms <90ms 2.82v vin > 3.75v 3.75v bat < 2.82v (3.1v - 0.28v) when vin < 3.51v (3.75v - 0.24v) disable wake up suddenly
RT5021 39 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? suspend mode when usus = 1, the charger will enter suspend mode. in suspend mode, chg pin is high impedance and iusus(max) < 300 a. charging current decision the charge current can be set according to the i 2 c register a8.iseta [3:0] setting : RT5021 allows user to set the battery charge current level and the list as below. the default value is 0.5a. code bat charge current code bat charge current code bat charge current code bat charge current 0000 0.1a 0001 0.2a 0010 0.3a 0011 0.4a 0100 0.5a 0101 0.6a 0110 0.7a 0111 0.8a 1000 0.9a 1001 1a 1010 1.1a 1011 1.2a iseta [3:0] 1100 1.2a 1101 1.2a 1110 1.2a 1111 1.2a 1 fault-time icharge example : if the sensing battery temperature is hot or cold, the charge current will reduce to half charge current. so, the fault-time will increase to be double. jeita battery temperature standard cv regulation voltage will be changed in the following battery temperature ranges : 0 c to 10 c and 45 c to 60 c. this function can be disabled by a9.vseth and a9.vsetc. cc regulation current will be changed in the following battery temperature ranges : 0 c to 10 c and 45 c to 60 c. this function can be disabled by a9.iseth and a9.isetc. fault-time during the fast charge phase, several events may increase the charging time. for example, the system load current may have activated the appm loop which reduces the available charging current or the device has entered thermal regulation because the ic junction temperature has exceeded t reg . however, once the duration exceeds the fault-time, the chg output pin will flash at approximately 4hz to indicate a fault condition and the charge current will be reduced to about 1ma. there are four methods to release the fault-time : ` re-plug power ` toggle en ` enter/exit suspend mode ` remove battery ` ovp the fault-time is inverse proportional to the charger current.
RT5021 40 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? cold hot 0c 10c 45c 60c vsetc = 0 isetc = 0 4.2v 4.05v i chg 4.2v vsetc = 0 0.5 x i chg 4.05v i chg 0.5 x i chg isetc = 0 4.2v 4.05v i chg 0.5 x i chg vsetc = 1 isetc = 1 4.2v 4.05v i chg 0.5 x i chg vsetc = 1 isetc = 1 vseth = 0 iseth = 0 vseth = 1 iseth = 1 vseth = 1 iseth = 1 iseth = 0 vseth = 0 ts ts ts ts jeita = 0 vseth = 0 vsetc = 0 iseth = 0 isetc = 0 jeita = 0 vseth = 1 vsetc = 0 iseth = 1 isetc = 0 jeita = 0 vseth = 1 vsetc = 1 iseth = 1 isetc = 1 jeita = 0 vseth = 0 vsetc = 1 iseth = 0 isetc = 1 4.2v 4.05v i chg 0.5 x i chg ts vseth = 1 iseth = 1 4.2v 4.05v i chg 0.5 x i chg vseth = 0 iseth = 0 0c 10c 45c 60c ts jeita = 1 vseth = 1 vsetc = x iseth = 1 isetc = x jeita = 1 vseth = 0 vsetc = x iseth = 0 isetc = x
RT5021 41 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? battery pack temperature monitoring the battery pack temperature monitoring function can be realized by connecting the ts pin to an external negative temperature coefficient (ntc) thermal resistor to prevent over temperature condition. charging is suspended when the voltage at the ts pin is out of normal operating range. the internal timer is then paused, but the value is maintained. when the ts pin voltage returns to normal operating range, charging will resume and the safe charge timer will continue to count down from the point where it was suspended. note that although charging is suspended due to the battery pack temperature fault, the chg pin will flash at 0.5hz and indicate charging. the 3.3v at vp pin is buffered by the RT5021 once it is in charging state or its pmu part is enabled. if a 100k ntc thermal resistor is used, the a0.tssel bit should be set to ? 1 ? . if a 10k ntc thermal resistor is used, the a0.tssel bit should be set to ? 0 ? . the tssel bit determines the ts threshold levels for 0 c and 60 c. it also defines the ts threshold levels used in jeita operation. the choosing method of r1 and r2 to meet battery temperature monitoring shows as below. case 2 : tssel = l (for 10k ntc) : figure 5 case 1 : tssel = h (for 100k ntc) : 0.74 x vp + - + - vp too cold too hot ts r1 r2 r ntc vp 0.28 x vp figure 4 --------------------------------------- (1) ----------------------------------------- (2) ---------------------------------------------- (3) ------------------------------------------ (1) ------------------------------------------ (2) ------------------------------------------------- (3) () ? ? ? cold cold hot hot cold hot hot cold cold cold cold r2 + r = 0.6 r+r1+r2 r2 + r = 0.28 r+r1+r2 form (1), (2) r1 = 0.9 r r r2 = 0.388 r1 r if r2 < 0 r = 0.6 r+r1 form (3) r r1 = r 0.6 too cold temperature r cold = r ntc too hot temperature r hot = r ntc too cold temperature r cold = r ntc too hot temperature r hot = r ntc cold cold hot hot cold hot hot cold cold cold cold r2 r = 0.74 rr1r2 r2 r = 0.28 rr1r2 form (1), (2) rr r1 = 2.457 r2 = 0.389 r1 r if r2 < 0 r = 0.74 rr1 form (3) r r1 = r 0.74 + ++ + ++ ? ? + ? 0.6 x vp + - + - vp too cold too hot ts r1 r2 r ntc vp 0.28 x vp
RT5021 42 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? the control temperature used in jeita operation the above calculation gives r1 and r2. jeita control thresholds for full charging current and 4.2v regulation voltage are at ts/vp ratio = 32% and 52% (for tssel = l), 35% and 64% (for tssel = h). with the ratio, the corresponding ntc thermistor resistances from the resistors in the voltage divider circuit can be obtained. according to the ntc resistances, the corresponding temperatures can be found. the two te mperatures are the control temperatures used in jeita operation. operation state diagram for ts pin (tssel = h) any state 74% x v vp < v ts < 2.85v or v ts < 28% x v vp no yes v ts > 2.85v no yes ts fault state i chg = 0a chg 4hz flash rate battery remove state i chg = 0a chg 4hz flash rate power switch for the charger, there are three power scenarios : ` when a battery and an external power supply (usb or adapter) are connected simultaneously if the system required load exceeds the input current limit, the battery will be used to supplement the current to the load. however, if the system load is less than the input current limit, the excess power from the external power supply will be used to charge the battery. ` when only the battery is connected to the system the battery provides the power to the system. ` when only an external power supply is connected to the system the external power supply provides the power to the system. input dpm mode for the charger, the input voltage is monitored when usb100 or usb500 is selected. if the input voltage is lower than vdpm, the input current limit will be reduced to stop the input voltage from dropping further. this can prevent the ic from damaging improperly configured or inadequately designed usb sources. if vin charger type is detected as sdp, the dpm function always is enabled. for other types, the dpm function always is disabled but user can set a0.endpm to turn on the dpm function. enable the charger vin dpm function. but if vin charger type is detected as sdp (chg_typ [2:0] = 000), the dpm function always is enabled. 0 : vin dpm function disabled. endpm 1 : vin dpm function enabled.
RT5021 43 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? appm mode once the sum of the charging current and system load current is higher than the maximum input current limit, the sys pin voltage will be reduced. when the sys pin voltage is reduced to v appm , the RT5021 will automatically operate in appm mode. in this mode, the charging current is reduced while the sys current is increased to maintain system output. in appm mode, the battery termination function is disabled. appm profile 1.5a mode : i sys v sys i vin i bat t1, t7 0 sys regulation voltage chg_max chg_max t2, t6 < i vi n_oc ? chg_max sys regulation voltage i sys + chg_max chg_max t3, t5 > i vi n_oc ? chg_max < i vin_oc auto charge voltage threshold v in_oc v in_oc ? i sys t4 > i vin_oc v bat ? i bat x r ds(on) v in_oc i sys ? i vin_oc 1a 0 -1a 2a 3a -2a -3a 5v 5v 4.15v 4.2v i bat i sys i vin t1 t2 t3 t4 t5 t6 t7 v bat v in v sys v appm 500ma mode : 0.25a 0 -0.25a 0.5a 0.75a -0.5a -0.75a 5v 4.15v 4.2v i bat i sys i usb t1 t2 t3 t4 t5 t6 t7 v bat v usb v sys v appm 5v
RT5021 44 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? i sys v sys i usb i bat t1, t7 0 sys regulation voltage chg_max chg_max t2, t6 < i vi n_oc (u sb) ? chg_max sys regulation voltage i sys + chg_max chg_max t3, t5 > i vi n_oc (u sb) ? chg_max < i vin_oc (usb) auto charge voltage threshold i vi n_oc (usb) i vin_oc (usb) ? i sys t4 > i vin_oc (usb) v bat ? i bat x r ds(on) i vi n_oc (usb) i sys ? i vin_oc (usb) battery supplement mode short circuit protect in appm mode, the sys voltage will continue to drop if the charge current is zero and the system load increases beyond the input current limit. when the sys voltage decreases below the battery voltage, the battery will kick in to supplement the system load until the sys voltage rises above the battery voltage. while in supplement mode, there is no battery supplement current regulation. however, a built-in short circuit protection feature is available to prevent any abnormal current situation. while the battery is supplementing the load, if the difference between the battery and sys voltage exceeds the short circuit threshold voltage, sys will be disabled. after a short circuit recovery time, t short_r , the counter will be restarted. in supplement mode, the battery termination function is disabled. note that the battery supply mode exiting condition is v bat ? v sys < 0v. thermal regulation and thermal shutdown the charger provides a thermal regulation loop function to monitor the device temperature. if the die temperature rises above the regulation temperature, t reg , the charge current will automatically be reduced to lower the die temperature. however, in certain circumstances (such as high vin, heavy system load, etc) even with the thermal loop in place, the die temperature may still continue to increase. in this case, if the temperature rises above the thermal shutdown threshold, t sd , the internal switch between vin and sys will be turned off. the switch between the battery and sys will remain on, however, to allow continuous battery power to the load. once the die temperature decreases by t sd , the internal switch between vin and sys will be turned on again and the device returns to normal thermal regulation. the internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures.
RT5021 45 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? i 2 c waveform information sda scl t f t low t hd,sta t hd,dat t high t su,dat t su,sta t hd,sta t sp t buf t su,sto ps t r s r s t f t r s 0 1 a p lsb msb a assume address = m data for address = m data for address = m + n - 1 a data for address = m + 1 s 0 p assume address = m data for address = m data for address = m + n - 1 data for address = m + 1 sr slave address register address slave address data 1 r/w r/w data n lsb msb a a a a a a a a read n bytes from RT5021 lsb msb data 2 data n lsb msb lsb slave address register address data 1 data 2 msb msb lsb write n bytes to RT5021 driven by master, driven by slave (RT5021), start, repeat start stop, s sr p i 2 c interface RT5021 i 2 c slave address = 0010010 (7 bits). i 2 c interface supports fast mode (bit rate up to 400kb/s). the write or read bit stream (n 1) is shown below :
RT5021 46 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? type i : 10-bit slave address data format in 10-bit addressing, the slave address is sent in the first two bytes. the first byte begins with the special reserved address of 11110xx which indicates that 10-bit addressing is being used. type ii : 2-byte register address data format the register address is combined with 2-byte as below. when RT5021 and other i 2 c devices with 10-bit slave addressing (type i) or two-byte register addressing (type ii) coexist in one i 2 c bus, RT5021 need one dummy i 2 c write frame to reset the RT5021 internal i 2 c operation state. the below shows a dummy write frame example, that is to write RT5021 register a10 [7:0] = 00000000. master should ignore the write operation (this operation is invalid). after the dummy frame, the master can read/write formal i 2 c frame for RT5021 to get right operation. s 0 a slave address register address slave address sr a a 1 msb a a data 1 lsb 2-byte register address s x x r/w 1 1 1 1 0 x xack bit 0 ack bit 7 bit 8 bit 9 x x x x bit 0 lsb bit 9 msb 10-bit address x x x x x x x x x x x x msb lsb s a p read 2 bytes type i/type ii data. s a p s a p read RT5021 data. s a p s p s p write RT5021 data. write 2 bytes type i/type ii data. a s a p write 2 bytes type i/type ii data. s a p s a p read RT5021 data. s a p s p write RT5021 register a10[7:0] = 00000000 data. s p write RT5021 data. read 2 bytes type i/type ii data. a dummy i 2 c write frame. normal i 2 c read/write frame a a write RT5021 register a10[7:0] = 00000000 data. write RT5021 register a10[7:0] = 00000000 data. write RT5021 register a10[7:0] = 00000000 data.
RT5021 47 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? i 2 c register file address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning rst_p rst_c ovp7 reserved endpm tsd mod7 tssel default 1 0 0 x 0 0 0 1 a0 0x00 read/write r/w r/w r/w -- r/w r/w r r/w RT5021 would reset pmu-related regist ers under any one of the below two conditions : 1) vddi < 1.3v 2) (en pin = low and a0.rst_p = 1) in the 2 nd condition, RT5021 uses the register bit a0.rst_p to decide whether the pmu-related registers are reset or not when en pin goes low. 0 : don?t reset register (0x3 to 0x6) rst_p 1 : reset register (0x3 to 0x6). RT5021 would reset charge-related regist er under any one of the below three conditions : 1) vin < 4v 2) vddi < 1.3v 3) (bat < 3.1v) and (a0.rst_c = 1) in the 3 rd condition, RT5021 uses the register bit a0.rst_c to decide whether the charge-related registers are reset or not when bat < 3.1v. 0 : don?t reset register (0x7 to 0x9). rst_c 1 : reset register (0x7 to 0x9) ch7 allow user to select the ovp level by i 2 c interface 0 : 16v ovp ovp7 1 : 25v ovp enable the charger vin dpm function. but if vin charger type is detected as sdp (chg_typ [2:0] = 000), the dpm function always is enabled. 0 : vin dpm function disabled endpm 1 : vin dpm function enabled. report whether thermal shut down of pmu ever occurs. re set it by writing 0 into the bit or (vddi < 1.3v). 0 : thermal shutdown has not occurred. tsd 1 : thermal shutdown event ever occurs. report the result of ch7 mode detection. 0 : current source. mod7 1 : boost. ts/vp ratio setting for battery temperature. 0 : ts/vp = 60% (0c), 28% (60c) tssel 1 : ts/vp = 74% (0c), 28% (60c)
RT5021 48 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning err1 err2 err3 err4 err5 err6 err7 err8 default 0 0 0 0 0 0 0 0 a1 0x 01 read/write r/w r/w r/w r/w r/w r/w r/w r/w report whether the protection event of ch1 to ch8 ever occurs respectively. reset it by writing 0 into the bit or (vrtc < 1.6v). 0 : no protection event occurs. err1 to err8 1 : protection event ever occurs. address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning en5 e n6 en 8 e n7_dim7 [4:0] default 0 0 0 0 0 0 0 0 a2 0x02 read/write r/w r/w r/w r/w r/w r/w r/w r/w enable/disable ch5 0 : disable en5 1 : enable enable/disable ch6 0 : disable en6 1 : enable enable/disable ch8 0 : disable en8 1 : enable enable ch7 and define fb7 regulation voltage 00000 : ch7 turn off en7_dim7 [4:0] 00001 to11111 : ch7 turn on and dimming ratio : vfb7 = en7_dim7 [4 : 0] / 31 x 0.25v
RT5021 49 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning psm1 psm2 psm3 psm4 vout8 [3:0] default 1 1 1 1 1 1 0 0 a3 0x03 read/write r/w r/w r/w r/w r/w r/w r/w r/w define the ch1/2/3/4 ccm or pwm/psm switching operation. 0 : force pwm psm1 to psm4 1 : automatic pwm/psm switch operation ch8 regulation voltage can be selected by i 2 c interface. the default voltage is 2.8v. code voltage code voltage code voltage code voltage 0000 switch 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.5v vout8 [3:0] 1100 2.8v 1101 3.1v 1110 3.2v 1111 3.3v address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit bit0 (lsb) meaning vout1 [3:0] en1 fb2 [2:0] default 1 0 1 0 0 1 0 0 a4 0x04 read/write r/w r/w r/w r/w r/w r/w r/w r/w ch1 regulation voltage can be selected by i 2 c interface. the default voltage is 5v. code voltage code voltage code voltage code voltage 0000 3.6v 0001 3.7v 0010 3.8v 0011 3.9v 0100 4v 0101 4.5v 0110 4.6v 0111 4.7v 1000 4.8v 1001 4.9v 1010 5v 1011 5.1v vout1 [3:0] 1100 5.2v 1101 5.3v 1110 5.4v 1111 5.5v enable/disable ch1 when sequence id is seo#0. in seo#0, ch1 is not the power on/off sequence. in other sequence. ch1 is in sequence control and on/off by the pin en, not by the register bit en1. 0 : disable en1 1 : enable fb2 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb2 [2:0] 111 0.86v 1.935v 1.075v 3.5475v
RT5021 50 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb ) meaning flst fb3 [2:0] flst2 fb4 [2:0] default 1 1 0 0 1 1 0 0 a5 0x05 read/write r/w r/w r/w r/w r/w r/w r/w r/w used to control the chg pin status when the register bit a9. chgsten = 0. 1 : chg = high impedance. flst 0 : chg = low. fb3 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb3 [2:0] 111 0.86v 1.935v 1.075v 3.5475v used to control the chg2 pin status when the register bit a8. chg2sten = 0. 1 : chg2 = high impedance. flst2 0 : chg2 = low. fb4 regulation voltage can be selected by i 2 c interface. the default voltage is 0.8v. code vref if target = 1.8v if target = 1v if target = 3.3v 000 0.72v 1.62v 0.9v 2.97v 001 0.74v 1.665v 0.925v 3.0525v 010 0.76v 1.71v 0.95v 3.135v 011 0.78v 1.755v 0.975v 3.2175v 100 0.8v 1.8v 1v 3.3v 101 0.82v 1.845v 1.025v 3.3825v 110 0.84v 1.89v 1.05v 3.465v fb4 [2:0] 111 0.86v 1.935v 1.075v 3.5475v
RT5021 51 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning vout5 [3:0] vout6 [3:0] default 1 0 0 0 0 0 1 1 a6 0x06 read/write r/w r/w r/w r/w r/w r/w r/w r/w ch5 regulation voltage can be selected by i 2 c interface. the default voltage is 1.8v. code voltage code voltage code voltage code voltage 0000 ref 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.3v 1100 2.5v 1101 2.6v 1110 2.7v 1111 2.8v vout5 [3:0] note : vout5 [3:0] = 0000 (ref) means using external feedback network and fb5 regulation target is 0.8v 1.5% ch6 regulation voltage can be selected by i 2 c interface. the default voltage is 1.3v. code voltage code voltage code voltage code voltage 0000 switch 0001 1.1v 0010 1.2v 0011 1.3v 0100 1.4v 0101 1.5v 0110 1.6v 0111 1.7v 1000 1.8v 1001 2v 1010 2.2v 1011 2.5v vout6 [3:0] 1100 2.8v 1101 3.1v 1110 3.2v 1111 3.3v
RT5021 52 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit 1 bit 0 (lsb) meaning timer [3:0] ench usus isetu isetl default 0 1 0 0 0 0 0 0 a7 0x07 read/write r/w r/w r/w r/w r/w r/w r/w r/w timer [3:0] define fast charger safe charging time. fast charging timeout time = (timer [3:0] + 1) hours. the default voltage is 5 hours. note : pre-charge timeout time = fast charge time/8. enable charger 0 : enable charger ench 1 : disable charger vin suspend control 0 : no suspend usus 1 : suspend vin current limit setting : isetl isetu vin input current limit 0 0 95ma (default) 0 1 475ma 1 0 1a 1 1 1.5a isetu and isetl note: when charger type detection finds the charger is dedicated charging port (sony or apple charger), isetu/isetl would set to be 475ma automatically.
RT5021 53 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning tsht[1:0] mask_dpm chg2sten iseta [3:0] default 0 0 0 1 0 1 0 0 a8 0x08 read/write r/w r/w r/ w r/w r/w r/w r/w r/w set ts/vp threshold to monitor batte ry temperature for hot boundary. equivalent battery temperature code ts/vp ratio 10k ntc 100k ntc 00 28% 60c 60c 01 28.5% 58c 59c 10 29% 56c 57c tsht [1:0] 11 29.5% 54c 56c mask dpm function 0 : when dpm event change, int would be asserted. mask_dpm 1 : when dpm event change, int would not be asserted. used to control chg2 pin status. 0 : see flsh2 set. chg2sten 1 : base on charging status. chg2sten = 0 (a8.bit4 = 0) charging status chg2sten = 1 (a8.bit4 = 1) flst2 = 1 (a5.bit3 = 1) flst2 = 0 (a5.bit3 = 0) no charging/ charging finish high impedance (no flashing) pre-charge/ fast charge low abnormal (fault timer timeout, in thermal regulation, battery too cold or too hot 4hz (0.25s) high impedance low RT5021 allows user to set the battery charge current level and the list as below. the default value is 0.5a. code bat charge current code bat charge current code bat charge current code bat charge current 0000 0.1a 0001 0.2a 0010 0.3a 0011 0.4a 0100 0.5a 0101 0.6a 0110 0.7a 0111 0.8a 1000 0.9a 1001 1a 1010 1.1a 1011 1.2a iseta [3:0] 1100 1.2a 1101 1.2a 1110 1.2a 1111 1.2a
RT5021 54 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning jeita vseth vsetc iseth isetc chgsten int dpm default 0 0 0 0 0 1 0 0 a9 0x09 read/write r/w r/w r/w r/w r/w r/w r/w r bat charge current and regulation voltage control scheme. jeita = 0, it means the charger operation is automatic (jeita rule). jeita, vseth, vsetc, iseth, isetc jeita = 1, user can set the vseth/vsetc to decide the bat regulate voltage and set iseth/isetc to decide the bat charge current level. the control scheme is listed as below. used to control chg pin status. 0 : see flsh set. chgsten 1 : base on charging status. chgsten = 0 (a9.bit2 = 0) charging status chgsten = 1 (a9.bit2 = 1) flst = 1 (a5.bit7 = 1) flst = 0 (a5.bit7 = 0) no charging/ charging finish high impedance (no flashing) pre-charge/ fast charge 0.5hz (2s) abnormal (fault timer timeout, in thermal regulation, battery too cold or too hot 4hz (0.25s) high impedance low control the output of int open drain port. the bit value is inverted of int output. when interrupt events happen, int port goes low and this bit a9. int would be triggered to 1. micro-processor must write this bit to be 0 for making int go high. 0 : int = high int 1 : int = low the dpm bit is the charger vin dpm status bit. it means the charger dpm (vin falls and regulates at 4.35v) is activated or not. 0 : vin dpm not activated. 1 : vin dpm activated (working). dpm note : when pmu turns on, it would check the bit dpm and compare to the value 0. if it is different, int would be asserted. after pmu is on, once dpm bit toggles, int also asserts again.
RT5021 55 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ts meter [2:0] ts ts meter [2:0] = 011 0c 10c 45c 60c ts meter [2:0] = 001 ts meter [2:0] = 000 ts meter [2:0] = 100 ts meter [2:0] = 110 vp < 0.8v (vp uvlo) ts meter [2:0] = 010 address name register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning ts_meter [2:0] nobat eoc pgood thr safe default 0 0 0 0 0 0 0 0 a10 0x0a read/write r r r r r r r r reports the battery temperature and vp status by detecting the ts pin voltage. ts_meter [2:0] note : when pmu turns on, it would check ts_meter [2:0] and compare to the value 000. if it is different, int would be asserted. after pmu is on, once any bits of ts_meter [2:0] toggles, int also asserts again. means the battery installed or not. 0 : bat installed 1 : no battery installed (ts > 90% of vp) nobat note : when pmu turns on, it would check the bit nobat and compare to the value 0. if it is different, int would be asserted. after pmu is on, once nobat bit toggles, int also asserts again. end of charge (eoc) bit show the charge status. if eoc = 1 means the charger is in eoc status. 0 : during charging 1 : charging done or recharging after termination eoc note: when pmu turns on, it would check the bit eoc and compare to the value 0. if it is different, int would be asserted. after pmu is on, once eoc bit toggles, int also asserts again. pgood bit means the vin power status. input status pgood bit status vin < vuvlo 0 vuvlo < vin < vbat + vos_l 0 vbat + vos_h < vin < vovp 1 vin > vovp 0 pgood note : when pmu turns on, it would check the bit pgood and compare to the value 0. if it is different, int would be asserted. after pmu is on, once pgood bit toggles, int also asserts again.
RT5021 56 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? thr bit can be let user to monitor the therma l regulation function is working or not. 0 : thermal regulation is not working 1 : thermal regulation is working thr note : when pmu turn on, it would check th e bit thr and compare to the value 0. if it is different, int would be asserted. af ter pmu is on, once thr bit toggles, int also asserts again. charger safety timer status. 0 : charger in charging or suspended by thermal loop 1 : safety timer expired safe note : when pmu turn on, it would check the bit safe and compare to the value 0. if it is different, int would be asserted. after pmu is on, once safe bit toggles, int also asserts again. address names register address bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) meaning chg_typ [2:0] reserved reserved chg_2det chg_1det chgrun default 0 0 0 x x 0 1 0 a11 0x0b read/write r r r -- -- r/w r/w r the chg_typ [2:0] is used to recode the charger type. code charger type code charger type 000 standard usb charger (sdp) 100 apple charger (1a) 001 sony charger -1 111 dedicated charger (dcp) 010 sony charger -2 chg_typ [2:0] 011 apple charger (0.5a) 110 charging downstream port (cdp) (high current host/hub) the chg_2det bit is used to enable the secondary charger detection (to distinguish cdp and dcp). default value is 0. set this bit value to 1 in order to enable charger detection. 0 : secondary charger detection disabled chg_2det 1 : secondary charger detection enable. the chg_1det bit is used to enable th e primary charger detection. default value is 1 (auto-detect charger type when vin plug in). toggle this bit value (set to 0 and then set 1) to re-enable charger detection. 0 : primary charger detection disabled. chg_1det 1 : primary charger detection enable. the chgrun bit is the charger detector st atus bit. it means the charger detection is running or not. 0 : charger detection not runing. 1 : charger detection running. chgrun note : when pmu turn on, it would check the bit chgrun and compare to the value 1. if it is different, int would be asserted. after pmu is on, once chgrun bit change from 1 to 0, int also asserts again.
RT5021 57 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 meaning rst_p rst_c ovp7 reserved endpm tsd mod7 tssel default 1 0 0 x 0 0 0 1 read/write r/w r/w r/w -- r/w r/w r r/w a0 0x00 reset condition a a a g a a h a meaning err1 err2 err3 err4 err5 err6 err7 err8 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a1 0x01 reset condition a a a a a a a a meaning en5 en6 en8 en7_dim7 [4:0] default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a2 0x02 reset condition b b b b b b b b meaning psm1 psm2 psm3 psm4 vout8 [3:0] default 1 1 1 1 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a3 0x03 reset condition c c c c c c c c meaning vout1 [3:0] en1 fb2 [2:0] default 1 0 1 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a4 0x04 reset condition c c c c b c c c meaning flst fb3[2:0] flst2 fb4[2:0] default 1 1 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a5 0x05 reset condition c c c c c c c c meaning vout5 [3:0] vout6 [3:0] default 1 0 0 0 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w a6 0x06 reset condition c c c c c c c c meaning timer [3:0] ench usus isetu isetl default 0 1 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a7 0x07 reset condition d d d d d d d d
RT5021 58 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 meaning tsht [1:0] mask_dpm chg2sten iseta [3:0] default 0 0 0 1 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a8 0x08 reset condition d d d d d d d d meaning jeita vseth vsetc iseth isetc chgsten int dpm default 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r a9 0x09 reset condition d d d d d d e d meaning ts_meter [2:0] nobat eoc pgood thr safe default 0 0 0 0 0 0 0 0 read/write r r r r r r r r a10 0x0a reset condition i i i i j j j j meaning chg_typ [2:0] reserved reserved chg_ 2det chg_ 1det chgrun default 0 0 0 x x 0 1 0 read/write r r r -- -- r/w r/w r a11 0x0b reset condition k k k g g f f l i 2 c register reset condition : a. in addition to a0.bit 1 and a0.bit4, the bits of a0 and a1 (register 0x0, 0x1) reset only when (vrtc < 1.6v). b. the bits of a2 (register 0x2) and a4.bit3 reset when (en pin = low) or (vddi < 2.4v) or (bat < 1.3v) or (temperature > 125 c) c. in addition to a4.bit3, pmu settings (a3 to a6, register 0x3 to 0x6) reset when (en pin = low and a0.rst_p = 1) or (vddi < 1.3v) vddi < 1.3v en pin a0.rst_p bit ==> reset pmu setting true x x (don?t care) reset low 1 reset high 1 not reset low 0 not reset false (vddi > 1.3v) high 0 not reset d. in addition to a9.bit 1, charger settings (a7 to a9, registers (0x7 to 0x9) reset when (vin < 4v) or (vddi < 1.3v) or ((bat < 3.1v) and (a0.rst_c = 1))
RT5021 59 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? chg chg2 chgsten = 0 chg2sten = 0 charging status chgsten = 1 a5. bit7 = 1 a5. bit7 = 0 chg2sten = 1 a5. bit3 = 1 a5. bit3 = 0 no charging/charging finish high impedance (no flashing) high impedance (no flashing) pre-charge/fast charge 0.5hz (2s) low abnormal (fault timer timeout, in thermal regulation, battery too cold or too hot) 4hz (0.25s) high impedance low 4hz(0.25s) high impedance low chg signal status vddi < 1.3v vin > 4v a0.rst_c bit (bat < 3.1v) ==> reset charger setting true (vddi < 1.3v) x x x reset false (vddi > 1.3v) false (vin < 4v) x x reset false (vddi > 1.3v) true (vin > 4v) 1 true reset false (vddi > 1.3v) true (vin > 4v) 1 false not reset false (vddi > 1.3v) true (vin > 4v) 0 true not reset false (vddi > 1.3v) true (vin > 4v) 0 false not reset e. (en pin = low) or (vddi < 1.3v) f. charger type detection a11 (registers 0xb) reset when (vin < 4v) or (vddi < 1.3v) g. always reset. h. a0.bit1 will be reset when (en pin = low) or (vddi < 2.4v) or (bat < 1.3v) or (pmu protection occur) or (temperature < 125 c). i. a0.bit1 will be reset when (en pin = low) or (vddi < 2.4v) or (bat < 1.3v) or (in addition to ch7 ovp, pmu protection occur) or (temperature < 125 c). j. reference page-54 a10 explanation. k. a11.bit7 to bit5 will be rewritten after charging type detects finish. l. a11.bit0 keeps high during charging type detecting.
RT5021 60 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? ntc thermistor order detection vref ready pmu enabled (en = h) or vin plug-in (charger start) vp buffer enabled vp vp > 2.97v vp_ready latch ntc detection result reset ntc detection result and issue next time to re-detect 10s ntc detection
RT5021 61 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? usb charger detection primary charger type detection (chg_1det) : detection time 200ms yes dedicated or high current host/hub standard usb port uvlo < vin < ovp & vin - vbat > 50mv & 30msec deglitch time initial state usus = 0 ench = 0 isetl = 0 isetu = 0 chg_1det = 1 chg_2det = 0 no no set 0.5a mode usus = 0 ench = 0 isetl = 0 isetu = 1 system is wake-up then disable wake-up function and set charging type. set charger condition by i 2 c data contact detect yes > 512ms data contact ok write dcd_t = 1 yes no yes d+ = vdp_src d- > vdat_ref & d- RT5021 62 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? secondary charger type detection (chg_2det) set chg_2det = 1 wait 300ms read 0x9 status chg_typ [2:0] = 101 chg_typ [2;0] = 110 dedicated charger detected (dcp) high current host/hub detected (cdp) yes yes no reset chg_2det = 0 d+/d- impedance of standard usb host/charging downstream port. apple charger, sony charger, and dedicated charger : d+ 3.6v 300k 14.25k to 24.8k d- 3.6v 300k 14.25k to 24.8k d+ 5v 75k 49.9k d- 5v 43.2k (for 1a) 49.9k d+ 5v 5.1k 10k d- 5v 5.1k 10k d+ 5v 1.554k d- 2.155k 0.5a d+ 5v 2m (min) d- 2m (min) 75k (for 0.5a) standard usb host charging downstream port apple charger sony charger sony charger-2 dedicated charger
RT5021 63 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-40l 5x5 package, the thermal resistance, ja , is 27.5 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (27.5 c/w) = 3.64w for wqfn-40l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout consideration for the best performance of the RT5021, the following pcb layout guidelines must be strictly followed. ` place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. ` keep the main power traces as wide and short as possible. ` the switching node area connected to lx and inductor should be minimized for lower emi. ` place the feedback components as close as possible to the fb pin and keep these components away from the noisy devices. ` connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. ` to make ch1 and whole chip stable, the power path from the pvd1 pin to its output capacitors must be as short ( 1mm is better) and wide as possible. ` to make ch4 and ch5 stable, the power path from the pvd45 pin to its input capacitors must be as short ( 1mm is better) and wide as possible. figure 6. derating curve of maximum power dissipation 0.0 0.8 1.6 2.4 3.2 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT5021 64 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? figure 7. pcb layout guide l1 r16 l3 d5 d4 c19 l7 l2 r7 c10 c12 l4 c23 l5 d2 vout_ch1 vout_ch4 vout_ch3 vout_ch2 vsys gnd gnd vout_ch7 gnd lx should be connected to inductor by wide and short trace, and keep sensitive components away from this trace. connect the exposed pad to a ground plane. place the feedback components as close as possible to the fb pin and keep away from noisy devices. input/output capacitors must be placed as close as possible to the input/output pins. c4 vout_ch6 d3 c21 c3 vsys vsys c22 c11 r8 d6 d7 vsys gnd c24 vsys gnd vout_ch8 gnd gnd gnd vout_ch5 c18 r4 r3 c7 c6 c5 r1 r2 rntc r6 r5 c9 c8 c2 c1 c14 c25 c26 c17 wake lx1 pvd6 vo6 lx7 fb7 pvd7 pvd1 vp pvd2 fb3 scl vo8 fb2 vo2 lx2a lx2b ts 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 fb4 seq lx4 en pvd45 lx5 vo5/fb5 pvd8 sda vrtc dn dp vin sys sys bat bat pvd3 lx3 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 gnd chg2 chg int c27 c28 output capacitor must be placed as close as possible to the output pin.
RT5021 65 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? protection type threshold (typical) refer to electrical spec. protection methods pmu shutdown delay time reset method sys uvlo sys < 1.5v pmu shutdown. no-delay en1234 pin set to low or sys > 2.1v ovp vddm > 6v automatic reset at vddm < 5.85v 100ms vddi power reset or en1234 pin set to low vddi uvlo vddm < 2.4v pmu shutdown. no-delay vddi power reset or en1234 pin set to low current limit n-mosfet peak current > 3a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi power reset or en1234 pin set to low pvd1 ovp pvdd1 > 6v n-mosfet off, p-mosfet off. no-delay vddi power reset or en1234 pin set to low pvd1 uvp --1 pvdd1 < (vsys ? 0.8v) or pvdd1 < 1.28v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddi power reset or en1234 pin set to low pvd1 uvp --2 after pre-charge (pvd1 uvp-2 : fb1 < 0.4v after pre-charge) n-mosfet off, p-mosfet off no-delay vddi power reset or en1234 pin set to low ch1 step-up pvd1 over load (ol) target ? 0.6v target voltage is defined in a4.vout1 [3:0] pmu shutdown when ol occur each cycle until 100ms. 100ms vddi power reset or en1234 pin set to low cu rrent limit both p-mosfet (pvd2 ? lx2a) and n-mosfet (lx2b ? gnd) peak current > 2a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi power reset or en1234 pin set to low vo2 ovp pvdd1 > 6v n-mosfet off, p-mosfet off. no-delay vddi power reset or en1234 pin set to low fb2 uvp fb2 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. no-delay vddi power reset or en1234 pin set to low ch2 ste p-up/do wn fb2 over load target ? 0.1v (target voltage is the chosen one in a4.fb2 [2:0]) pmu shutdown when ol occur each cycle until 100ms. 100ms vddi power reset or en1234 pin set to low cu rrent limit p-mosfet peak current > 1.8a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi power reset or en1234 pin set to low fb3 uvp fb3 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. no-delay vddi power reset or en1234 pin set to low ch3 step-down fb3 over load target ? 0.1v (target voltage is the chosen one in a5.fb3 [2:0]) pmu shutdown when ol occur each cycle until 100ms. 100ms vddi power reset or en1234 pin set to low
RT5021 66 ds5021-01 april 2013 www.richtek.com copyright 2013 richtek technology corporation. all rights reserved. is a registered trademark of ri chtek technology corporation. ? protection type threshold (typical) refer to electrical spec. protection methods pmu shutdown delay time reset method current limit p-mosfet peak current > 1.8a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi po wer reset or en1234 pin set to low fb4 uvp fb4 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. no-delay vddi po wer reset or en1234 pin set to low ch4 step-down fb4 over load targ et ? 0.1v (target voltage is the chosen one in a5.fb4 [2:0]) pmu shutdown when ol occur each cycle until 100ms. 100ms vddi po wer reset or en1234 pin set to low current limit p-mosfet peak current > 1.5a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi po wer reset or en1234 pin set to low vo5 uvp pvd5 uvp : fb5 < 0.4v after soft-start end n-mosfet off, p-mosfet off. no-delay vddi po wer reset or en1234 pin set to low target voltage is the chosen one in a6.vout5 [3:0] = 0000 (fb5 = 0.8v) target voltage is the chosen one in a6.vout5 [3:0] = 0001 to 0111 ch5 step-down vo5 over load target voltage is the chosen one in a6.vout5 [3:0] = 0111 to 1111 pmu shutdown when ol occur each cycle until 100ms. 100ms vddi po wer reset or en1234 pin set to low ch6 ldo max. output current (current limit) p-mosfet current > 0.45a (pvd6 = 1.5v, vo6 = 1.3v) p-mosfet off. 100ms vddi po wer reset or en1234 pin set to low current limit (step-up mode) n-mosfet current > 0.8a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddi po wer reset or en1234 pin set to low pvdd7 > 16v (a0.ovp7 = 0) ch7 wled pvdd7 ovp pvdd7 > 25v (a0.ovp7 = 1) n-mosfet off, p-mosfet off. shutdown ch7 by self no-delay vddi power reset and a2.en7_dim7 [4:0] reset or en1234 pin set to low ch8 ldo max. output current (current limit) p-mosfet current > 0.45a (pvd6 = 3v, vo6 = 2.5v) p-mosfet off. 100ms vddi po wer reset or en1234 pin set to low thermal thermal shutdown temperature > 155 c all channels stop switching no-delay temperature < (155 ? 20) c vin uvlo vin < 3.3v no-charge no-delay no latch vi n vin ovp vin > 6.5v no-charge no-delay no latch
RT5021 67 ds5021-01 april 2013 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 40l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2 d e d2 e2 l b a a1 a3 e 1 see detail a

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